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| Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparators ADCMP604/ADCMP605 FEATURES Fully specified rail to rail at VCC = 2.5 V to 5.5 V Input common-mode voltage from -0.2 V to VCC + 0.2 V Low glitch LVDS-compatible output stage 1.6 ns propagation delay 37 mW at 2.5 V Shutdown pin Single-pin control for programmable hysteresis and latch Power supply rejection > 60 dB -40C to +125C operation FUNCTIONAL BLOCK DIAGRAM VCCI VCCO (ADCMP605 ONLY) VP NONINVERTING INPUT Q OUTPUT ADCMP604/ ADCMP605 VN INVERTING INPUT LVDS Q OUTPUT APPLICATIONS High speed instrumentation Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators Automatic test equipment (ATE) LE/HYS INPUT SDN INPUT (ADCMP605 ONLY) Figure 1. GENERAL DESCRIPTION The ADCMP604 and ADCMP605 are very fast comparators fabricated on Analog Devices, Inc.'s, proprietary XFCB2 process. This family of comparators is exceptionally versatile and easy to use. Features include an input range from VEE - 0.5 V to VCC + 0.2 V, low noise, LVDS-compatible output drivers, and TTL/CMOS latch inputs with adjustable hysteresis and/or shutdown inputs. The devices offer 1.5 ns propagation delays with 1 ps rms random jitter (RJ). Overdrive and slew rate dispersion are typically less than 50 ps. A flexible power supply scheme allows the devices to operate with a single +2.5 V positive supply and a -0.5 V to +3.0 V input signal range up to a +5.5 V positive supply with a -0.5 V to +6 V input signal range. Split input/output supplies, with no sequencing restrictions on the ADCMP605, support a wide input signal range with greatly reduced power consumption. The LVDS-compatible output stage is designed to drive any standard LVDS input. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. High speed latch and programmable hysteresis features are also provided in a unique single-pin control option. The ADCMP604 is available in a 6-lead SC70 package. The ADCMP605 is available in a 12-lead LFCSP. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved. 05916-001 ADCMP604/ADCMP605 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Timing Information ......................................................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Application Information................................................................ 10 Power/Ground Layout and Bypassing..................................... 10 LVDS-Compatible Output Stage .............................................. 10 Using/Disabling the Latch Feature........................................... 10 Optimizing Performance........................................................... 10 Comparator Propagation Delay Dispersion ........................... 10 Comparator Hysteresis .............................................................. 11 Crossover Bias Points................................................................. 12 Minimum Input Slew Rate Requirement ................................ 12 Typical Application Circuits ......................................................... 13 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 14 REVISION HISTORY 10/06--Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADCMP604/ADCMP605 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VCCI = VCCO = 3.0 V, TA = 25C, unless otherwise noted. Table 1. Parameter DC INPUT CHARACTERISTICS Voltage Range Common-Mode Range Differential Voltage Offset Voltage Bias Current Offset Current Capacitance Resistance, Differential Mode Resistance, Common Mode Active Gain Common-Mode Rejection Ratio Symbol VP, VN Conditions VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V Min -0.5 -0.2 -5.0 -5.0 -2.0 -0.1 V to VCC -0.5 V to VCC + 0.5 V AV CMRR VCCI = 2.5 V, VCCO = 2.5 V, VCM = -0.2 V to +2.7 V VCCI = 2.5 V, VCCO = 5.5 V, RHYS = 200 100 50 50 < 0.1 Typ Max VCC + 0.2 VCC + 0.2 VCC +5.0 +5.0 2.0 7500 4000 Unit V V V mV A A pF k k dB dB dB mV VOS IP, IN CP, CN 2 1 750 370 62 Hysteresis LATCH ENABLE PIN CHARACTERISTICS (ADCMP605 Only) VIH VIL LIH IOL HYSTERESIS MODE AND TIMING (ADCMP605 Only) Hysteresis Mode Bias Voltage Minimum Resistor Value Hysteresis Current Latch Setup Time Latch Hold Time Latch-to-Output Delay Latch Minimum Pulse Width SHUTDOWN PIN CHARACTERISTICS (ADCMP605 Only) VIH VIL IIH IOL Sleep Time Wake-Up Time DC OUTPUT CHARACTERISTICS Differential Output Voltage Level VOD Common-Mode Voltage Peak-to-Peak Common-Mode Output Hysteresis is shut off Latch mode guaranteed VIH = VCCO + 0.2 V VIL = 0.4 V 2.0 -0.2 -6 -0.1 +0.4 VCC +0.8 +6 +0.1 V V A mA tS tH tPLOH, tPLOL tPL Current sink -1A Hysteresis = 120 mV Hysteresis = 120 mV VOD = 50 mV VOD = 50 mV VOD = 50 mV VOD = 50 mV 1.145 55 -20 1.25 1.35 110 -10 -2 2.7 20 24 V k A ns ns ns ns tSD tH VOD VOD VOC VOC(p-p) Comparator is operating Shutdown guaranteed VIH = VCC VIL = 0 V 10% output swing VOD = 50 mV, output valid VCCO = 2.5 V to 5.5 V RLOAD = 100 RLOAD = 100 RLOAD = 100 RLOAD = 100 2.0 -0.2 -6 +0.4 VCCO +0.6 +6 -0.1 1.4 25 245 1.125 350 445 50 1.375 50 V V A mA ns ns mV mV V mV Rev. 0 | Page 3 of 16 ADCMP604/ADCMP605 Parameter AC PERFORMANCE 1 Rise Time /Fall time Propagation Delay Propagation Delay Skew--Rising to Falling Transition Propagation Delay Skew--Q to QB Overdrive Dispersion Common-Mode Dispersion Input Bandwidth Minimum Pulse Width POWER SUPPLY Input Supply Voltage Range Output Supply Voltage Range Positive Supply Differential (ADCMP605) Positive Supply Current (ADCMP604) Input Section Supply Current (ADCMP605) Output Section Supply Current (ADCMP605) Power Dissipation Power Supply Rejection Ratio Shutdown Mode ICCI Shutdown Mode ICCO 1 Symbol tR, tF tPD tPINSKEW Conditions 10% to 90% VCC = 2.5 V to 5.5 V, VOD = 50 mV VCC = 2.5 V , VOD = 10 mV VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V 10 mV < VOD < 125 mV VCM = -0.2 V to VCC + 0.2 V Min Typ 600 1.6 3.0 70 70 1.6 250 500 1.3 Max Unit ps ns ns ps ps ns ps MHz ns PWMIN VCC = 2.5 V to 5.5 V PWOUT = 90% of PWIN 2.5 2.5 -3 -5.5 VCCI VCCO VCCI - VCCO VCCI - VCCO IVCC IVCCI IVCCO PD PSRR Operating Nonoperating VCC = 2.5 V to 5.5 V VCCI = 2.5 V to 5.5 V VCCO = 2.5 V to 5.5 V VCC = 2.5 V VCC = 5.5 V VCCI = 2.5 V to 5.5 V VCCI = 2.5 V to 5.5 V VCCI = 2.5 V to 5.5 V 15 1 15 37 91 -50 160 -30 5.5 5.5 +3 +5.5 21 3 22 2.75 50 110 650 +30 V V V V mA mA mA mA mW mW dB A A VIN = 100 mV square input at 50 MHz, VOD = 50 mV, VCM = 1.25 V, VCCI = VCCO = 2.5 V, unless otherwise noted. Rev. 0 | Page 4 of 16 ADCMP604/ADCMP605 TIMING INFORMATION Figure 2 illustrates the ADCMP604/ADCMP605 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2. 1.1V LATCH ENABLE tS tH tPL DIFFERENTIAL INPUT VOLTAGE VIN VOD VN VOS tPDL Q OUTPUT tPLOH 50% tPDH tF 50% tPLOL tR Figure 2. System Timing Diagram Table 2. Timing Descriptions Symbol tPDH tPDL tPLOH tPLOL tH tPL tS tR tF VOD Timing Input to output high delay Input to output low delay Latch enable to output high delay Latch enable to output low delay Minimum hold time Minimum latch enable pulse width Minimum setup time Output rise time Output fall time Voltage overdrive Description Propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output low-to-high transition. Propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output high-to-low transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition. Minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs. Minimum time that the latch enable signal must be high to acquire an input signal change. Minimum time before the negative transition of the latch enable signal occurs that an input signal change must be present to be acquired and held at the outputs. Amount of time required to transition from a low to a high output as measured at the 20% and 80% points. Amount of time required to transition from a high to a low output as measured at the 20% and 80% points. Difference between the input voltages VA and VB. Rev. 0 | Page 5 of 16 05916-025 Q OUTPUT ADCMP604/ADCMP605 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltages Input Supply Voltage (VCCI to GND) Output Supply Voltage (VCCO to GND) Positive Supply Differential (VCCI - VCCO) Input Voltages Input Voltage Differential Input Voltage Maximum Input/Output Current Shutdown Control Pin Applied Voltage (HYS to GND) Maximum Input/Output Current Latch/Hysteresis Control Pin Applied Voltage (HYS to GND) Maximum Input/Output Current Output Current Temperature Operating Temperature, Ambient Operating Temperature, Junction Storage Temperature Range Rating -0.5 V to +6.0 V -0.5 V to +6.0 V -6.0 V to +6.0 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE -0.5 V to VCCI + 0.5 V (VCCI + 0.5 V) 50 mA -0.5 V to VCCO + 0.5 V 50 mA -0.5 V to VCCO + 0.5 V 50 mA 50 mA -40C to +125C 150C -65C to +150C JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type ADCMP604 6-lead SC70 ADCMP605 12-lead LFCSP 1 JA1 426 62 Unit C/W C/W Measurement in still air. ESD CAUTION Rev. 0 | Page 6 of 16 ADCMP604/ADCMP605 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 11 VEE 12 Q 10 Q Q1 6 Q VCCO 1 ADCMP604 VEE 2 VP 3 4 PIN 1 INDICATOR 9 VEE 8 LE/HYS 7 SDN VN 05916-002 TOP VIEW (Not to Scale) 5 VCCI /VCCO VCCI 2 VEE 3 ADCMP605 TOP VIEW (Not to Scale) Figure 3. ADCMP604 Pin Configuration Figure 4. ADCMP605 Pin Configuration Table 5. ADCMP604 (SC70-6) Pin Function Descriptions Pin No. 1 2 3 4 5 6 Mnemonic Q VEE VP VN VCCI/VCCO Q Description Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN. Negative Supply Voltage. Noninverting Analog Input. Inverting Analog Input. Input Section Supply/Output Section Supply. VCCI and VCCO shared pin. Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN. Table 6. ADCMP605 (LFCSP-12) Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 Heat Sink Paddle Mnemonic VCCO VCCI VEE VP VEE VN SDN LE/HYS VEE Q VEE Q VEE Description Output Section Supply. Input Section Supply. Negative Supply Voltage. Noninverting Analog Input. Negative Supply Voltage. Inverting Analog Input. Shutdown. Drive this pin low to shut down the device. Latch/Hysteresis Control. Bias with resistor or current for hysteresis; drive low to latch. Negative Supply Voltage. Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. Negative Supply Voltage. Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. The metallic back surface of the package is electrically connected to VEE. It can be left floating because Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired. Rev. 0 | Page 7 of 16 05916-003 VEE 5 VN 6 VP 4 ADCMP604/ADCMP605 TYPICAL PERFORMANCE CHARACTERISTICS VCCI = VCCO = 2.5 V, TA = 25C, unless otherwise noted. 800 600 400 VCC = 2.5V CURRENT (A) 1.60 1.50 1.40 OUTPUT (V) OUTPUT HI VCC = 5.5V 200 0 -200 -400 -600 05916-010 1.30 1.20 1.10 1.00 0.90 2.4 OUTPUT VCM OUTPUT LO 0 1 2 3 4 LE/HYS PIN (V) 5 6 7 2.9 3.4 4.4 3.9 VCC (V) 4.9 5.4 5.9 Figure 5. LE/HYS I/V Curve 200 150 100 850 800 750 Figure 8. Output Level vs. VCC RISE/FALL (ps) CURRENT (A) VCC = 2.5V 50 0 -50 -100 VCC = 5.5V 700 +125C 650 600 550 500 450 +25C -40C 05916-006 -1 0 1 2 3 4 SDN PIN (V) 5 6 7 2.80 3.20 3.60 4.00 4.40 4.80 VCCO (Volts) 5.20 5.60 6.00 Figure 6. SDN I/V Curve 10 +125C 8 6 4 2 +25C -40C Figure 9. Output Rise/Fall Time vs. VCCO 250 200 HYSTERESIS (mV) 150 IB (A) 0 -2 -4 -6 -8 05916-009 100 VCC = 2.5V 50 VCC = 5.5V -0.5 0.0 0.5 1.0 1.5 2.0 VCM AT VCC = 2.5V 2.5 3.0 3.5 50 100 150 200 250 300 350 400 HYSTERESIS RESISTOR (k) 450 500 Figure 7. Input Bias Current vs. Input Common-Mode Voltage Figure 10. Hysteresis vs. RHYS Rev. 0 | Page 8 of 16 05916-008 -10 -1.0 0 05916-007 -150 400 2.40 05916-011 -800 -1 ADCMP604/ADCMP605 350 300 250 +125C 0.44 0.43 ADCMP605 - OUTPUT SWING VS VCC 0.42 HYSTERESIS (mV) +25C 200 150 100 50 0 -40C OUTPUT SWING (V) 05916-012 0.41 0.40 0.39 0.38 0.37 05916-013 0 -2 -4 -6 -8 -10 -12 HYS PIN CURRENT (A) -14 -16 -18 0.36 2.4 3.4 4.4 VCC (V) 5.4 Figure 11. Hysteresis vs. Pin Current 3.5 1.425V Figure 14. Output Swing vs. VCC PROPAGATION DELAY (ns) 3.0 Q 2.5 2.0 PROPAGATION DELAY 1.5 Q 05916-004 1.0 0 10 20 30 40 50 60 OVER DRIVE (mV) 70 80 90 100 925.0mV 1.000ns/DIV Figure 12 . Propagation Delay vs. Input Overdrive 1.6 Figure 15. 50 MHz Output Voltage Waveform VCCO = 2.5 V 1.543V Q PROPAGATION DELAY RISE ns 1.5 DELAY (ns) PROPAGATION DELAY FALL ns 1.4 05916-005 1.3 -0.6 -0.2 0.2 0.6 1.0 1.4 1.8 VCM AT VCC (2.5V) 2.2 2.6 3.0 1.043V 1.000ns/DIV Figure 13. Propagation Delay vs. Input Common Mode Figure 16. 50 MHz Output Voltage Waveform VCCO = 5.5 V Rev. 0 | Page 9 of 16 05916-015 Q 05916-014 ADCMP604/ADCMP605 APPLICATION INFORMATION POWER/GROUND LAYOUT AND BYPASSING The ADCMP604/ADCMP605 comparators are very high speed devices. Despite the low noise output stage, it is essential to use proper high speed design techniques to achieve the specified performance. Because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or undesired hysteresis. Of critical importance is the use of low impedance supply planes, particularly the output supply plane (VCCO) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. It is also important to adequately bypass the input and output supplies. Multiple high quality 0.01 F bypass capacitors should be placed as close as possible to each of the VCCI and VCCO supply pins and should be connected to the GND plane with redundant vias. At least one of these should be placed to provide a physically short return path for output currents flowing back from ground to the VCC pin. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Parasitic layout inductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies. If the package allows, and the input and output supplies have been connected separately (VCCI VCCO), be sure to bypass each of these supplies separately to the GND plane. Do not connect a bypass capacitor between these supplies. It is recommended that the GND plane separate the VCCI and VCCO planes when the circuit board layout is designed to minimize coupling between the two supplies to take advantage of the additional bypass capacitance from each respective supply to the ground plane. This enhances the performance when split input/output supplies are used. If the input and output supplies are connected together for single-supply operation (VCCI = VCCO), then coupling between the two supplies is unavoidable; however, careful board placement can help keep output return currents away from the inputs. USING/DISABLING THE LATCH FEATURE The latch input is designed for maximum versatility. It can safely be left floating or it can be driven low by any standard TTL/CMOS device as a high speed latch. In addition, the pin can be operated as a hysteresis control pin with a bias voltage of 1.25 V nominal and an input resistance of approximately 7000 . This allows the comparator hysteresis to be easily controlled by either a resistor or an inexpensive CMOS DAC. Driving this pin high or floating the pin disables all hysteresis. Hysteresis control and latch mode can be used together if an open drain, an open collector, or a three-state driver is connected in parallel to the hysteresis control resistor or current source. Due to the programmable hysteresis feature, the logic threshold of the latch pin is approximately 1.1 V regardless of VCC. OPTIMIZING PERFORMANCE As with any high speed comparator, proper design and layout techniques are essential for obtaining the specified performance. Stray capacitance, inductance, inductive power and ground impedances, or other layout issues can severely limit performance and often cause oscillation. Large discontinuities along input and output transmission lines can also limit the specified pulsewidth dispersion performance. The source impedance should be minimized as much as is practicable. High source impedance, in combination with the parasitic input capacitance of the comparator, causes an undesirable degradation in bandwidth at the input, thus degrading the overall response. Thermal noise from large resistances can easily cause extra jitter with slowly slewing input signals. Higher impedances encourage undesired coupling. COMPARATOR PROPAGATION DELAY DISPERSION The ADCMP604/ADCMP605 comparators are designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mV to VCCI - 1 V. Propagation delay dispersion is the variation in propagation delay that results from a change in the degree of overdrive or slew rate (how far or how fast the input signal is driven past the switching threshold). Propagation delay dispersion is a specification that becomes important in high speed, time-critical applications, such as data communication, automatic test and measurement, and instrumentation. It is also important in event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed (Figure 17 and Figure 18). LVDS-COMPATIBLE OUTPUT STAGE Specified propagation delay dispersion performance is only achieved by keeping parasitic capacitive loads at or below the specified minimums. The outputs of the ADCMP604 and ADCMP605 are designed to directly drive any standard LVDScompatible input. Rev. 0 | Page 10 of 16 ADCMP604/ADCMP605 The ADCMP604 and ADCMP605 dispersion is typically < 1.6 ns as the overdrive varies from 10 mV to 125 mV. This specification applies to both positive and negative signals because each the ADCMP604 and ADCMP605 have substantially equal delays for positive-going and negative-going inputs and very low output skews. 500mV OVERDRIVE OUTPUT VOH VOL INPUT VOLTAGE VN VOS -VH 2 0 +VH 2 INPUT Figure 19. Comparator Hysteresis Transfer Function 05916-016 DISPERSION Q/Q OUTPUT Figure 17. Propagation Delay--Overdrive Dispersion INPUT VOLTAGE 1V/ns VN VOS 10V/ns The customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. One limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not symmetric about the threshold. The external feedback network can also introduce significant parasitics that reduce high speed performance and induce oscillation in some cases. The ADCMP605 comparator offers a programmable hysteresis feature that significantly improves accuracy and stability. Connecting an external pull-down resistor or a current source from the LE/HYS pin to GND, varies the amount of hysteresis in a predictable and stable manner. Leaving the LE/HYS pin disconnected or driving it high removes hysteresis. The maximum hysteresis that can be applied using this pin is approximately 160 mV. Figure 20 illustrates the amount of hysteresis applied as a function of external resistor value. Figure 11 illustrates hysteresis as a function of current. The hysteresis control pin appears as a 1.25 V bias voltage seen through a series resistance of 7 k 20% throughout the hysteresis control range. The advantages of applying hysteresis in this manner are improved accuracy, improved stability, reduced component count, and maximum versatility. An external bypass capacitor is not recommended on the HYS pin because it would likely degrade the jitter performance of the device and impair the latch function. As described in the Using/Disabling the Latch Feature section, hysteresis control need not compromise the latch function. Q/Q OUTPUT Figure 18. Propagation Delay--Slew Rate Dispersion COMPARATOR HYSTERESIS The addition of hysteresis to a comparator is often desirable in a noisy environment, or when the differential input amplitudes are relatively small or slow moving. The transfer function for a comparator with Hysteresis is shown in Figure 19. As the input voltage approaches the threshold (0.0 V, in this example) from below the threshold region in a positive direction, the comparator switches from low to high when the input crosses +VH/2. The new switching threshold becomes -VH/2. The comparator remains in the high state until the threshold, -VH/2, is crossed from below the threshold region in a negative direction. In this manner, noise or feedback output signals centered on 0.0 V input cannot cause the comparator to switch states unless it exceeds the region bounded by VH/2. 05916-017 DISPERSION Rev. 0 | Page 11 of 16 05916-018 10mV OVERDRIVE ADCMP604/ADCMP605 250 200 HYSTERESIS (mV) some predetermined point in the common-mode range, a crossover occurs. At this point, normally VCC/2, the direction of the bias current reverses and there are changes in measured offset voltages and currents. 150 MINIMUM INPUT SLEW RATE REQUIREMENT With the rated load capacitance and normal good PC Board design practice, as discussed in the Optimizing Performance section, these comparators should be stable at any input slew rate with no hysteresis. Broadband noise from the input stage is observed in place of the violent chattering seen with most other high speed comparators. With additional capacitive loading or poor bypassing, oscillation is observed. This oscillation is due to the high gain bandwidth of the comparator in combination with feedback parasitics in the package and PC board. In many applications, chattering is not harmful. 100 VCC = 2.5V 50 VCC = 5.5V 50 100 150 200 250 300 350 400 450 500 05916-026 0 HYSTERESIS RESISTOR (k) Figure 20. Hysteresis vs. RHYS Control Resistor CROSSOVER BIAS POINTS Rail-to-rail inputs of this type, in both op amps and comparators, have a dual front-end design. Certain devices are active near the VCC rail and others are active near the VEE rail. At Rev. 0 | Page 12 of 16 ADCMP604/ADCMP605 TYPICAL APPLICATION CIRCUITS 2.5V 2.5V TO 5V 0.1F INPUT 2k 10k 2k ADCMP604 CMOS OUTPUT 05916-019 82pF ADCMP605 LE/HYS LVDS OUTPUT 0.1F Figure 21. Self-Biased, 50% Slicer 150k 150k 2.5V TO 3.3V Figure 24 . Voltage-Controlled Oscillator LVDS 100 ADCMP604 LVDS 05916-020 2.5V Figure 22. LVDS to Repeater ADCMP604 2.5V TO 5V INPUT 1.25V 50mV LVDS PWM OUTPUT ADCMP605 INPUT 1.25V REF 10k 10k ADCMP601 DIGITAL INPUT 74VHC 1G07 LE/HYS 150k 10k 82pF LE/HYS 05916-023 05916-024 100k CONTROL VOLTAGE 0V TO 2.5V 05916-021 150k Figure 25. Oscillator and Pulse-Width Modulator Figure 23. Hysteresis Adjustment with Latch 2.5V TO 5V ADCMP605 DIGITAL INPUT 74AHC 1G07 LE/HYS HYSTERESIS CURRENT 10k Figure 26. Hysteresis Adjustment with Latch Rev. 0 | Page 13 of 16 05916-022 CONTROL VOLTAGE 0V TO 2.5V 10k ADCMP604/ADCMP605 OUTLINE DIMENSIONS 2.20 2.00 1.80 2.40 2.10 1.80 3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ EXPOSED PAD (BOTTOM VIEW) 12 MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 0.50 BSC 0.60 MAX 0.75 0.55 0.35 9 8 7 6 5 4 10 11 12 1 2 3 1.35 1.25 1.15 PIN 1 1.30 BSC 1.00 0.90 0.70 6 1 5 2 4 3 PIN 1 INDICATOR *1.45 1.30 SQ 1.15 0.65 BSC 1.10 0.80 0.40 0.10 0.46 0.36 0.26 1.00 0.85 0.80 SEATING PLANE 0.25 MIN 0.10 MAX 0.30 0.15 0.10 COPLANARITY SEATING PLANE 0.22 0.08 *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1 EXCEPT FOR EXPOSED PAD DIMENSION. COMPLIANT TO JEDEC STANDARDS MO-203-AB Figure 27. 6-Lead Thin Shrink Small Outline Transistor Package (SC70) (KS-6) Dimensions shown in millimeters Figure 28. 12-Lead Lead Frame Chip Scale Package (LFCSP-VQ) 3 mm x 3 mm Body, Very Thin Quad (CP-12-1) Dimensions shown in millimeters ORDERING GUIDE Model ADCMP604BKSZ-R21 ADCMP604BKSZ-REEL71 ADCMP604BKSZ-RL1 ADCMP605BCPZ-WP1 ADCMP605BCPZ-R21 ADCMP605BCPZ-R71 EVAL-ADCMP605BCPZ1 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 6-Lead Thin Shrink Small Outline Transistor Package (SC70) 6-Lead Thin Shrink Small Outline Transistor Package (SC70) 6-Lead Thin Shrink Small Outline Transistor Package (SC70) 12-Lead Lead Frame Chip Scale Package (LFCSP-VQ) 12-Lead Lead Frame Chip Scale Package (LFCSP-VQ) 12-Lead Lead Frame Chip Scale Package (LFCSP-VQ) Evaluation Board Package Option KS-6 KS-6 KS-6 CP-12-1 CP-12-1 CP-12-1 Branding G0Q G0Q G0Q G0K G0K G0K Z = Pb-free part. Rev. 0 | Page 14 of 16 ADCMP604/ADCMP605 NOTES Rev. 0 | Page 15 of 16 ADCMP604/ADCMP605 NOTES (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05916-0-10/06(0) Rev. 0 | Page 16 of 16 |
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